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Fundamentals of SuperFlash

SuperFlash® technology has enabled designers to create cost effective and high performance programmable SOC solutions through the use of SST's proprietary split-gate flash memory cell. With the scaling from 1µm technology node to 65nm technology node over the past 20-year history of the company, the memory cell maintains its split-gate structure, fundamental operation conditions, a simple array architecture thus simplifying design, low power and high performance, silicon CMOS compatibility with good scalability, and excellent reliability.

Split-Gate Structure:

In general, the split-gate cell consists of a floating gate, a select-gate which may also function as an erase-gate, a source, and a drain. This is a one-and-a-half transistors cell and its size is comparable to that of the traditional stacked-gate cell for a given technology node. The channel, split between the drain and source, is a series combination of the floating-gate and select-gate transistors. The select-gate portion of the channel isolates the floating gate-portion from the drain which prevents over-erase, a common issue found in stacked-gate memory cells. The split-gate memory is programmed using source side channel hot electron (SS CHE) injection and erased using poly-poly Fowler-Nordheim (FN) tunneling between floating and select-gates.

Fundamental Operating Principle:

The fundamental operation principle of split-gate cell have remained unchanged through many generations of process technology scaling.

The cell is read by applying reference voltages to the select gate via word line and to the drain via bit line while the source is grounded. Reference voltage applied on the word line turns on the select gate portion of the channel; the cell conducts current if the floating gate is erased (low threshold state). However, the cell is non-conductive if the floating gate is programmed (high threshold state). The conductive cell outputs logic "1" and the non-conductive cell outputs logic "0". The cell read through the control of the select transistor eliminates the "over erase" issue encountered in stacked-gate flash memory cell.

SuperFlash® cell programs using highly efficient SS CHE injection mechanism. During programming, a high voltage applied on the source capacitively couples to the floating-gate through floating-gate oxide to create a vertical electric field between floating-gate and channel. At the same time, a voltage slightly higher than the select transistor threshold is applied to the word-line. The extension of source and the drain voltages toward the thin gap between floating and select-gates creates a strong lateral electric field across the gap which generates hot electrons when the channel current flows through. Only a minute portion of these hot electrons with sufficient energy and right orientation (the "lucky" electrons) can hop over the silicon-oxide interface. But once hopped over, these lucky electrons will be almost 100% swept by the attractive electric field toward, and absorbed by, the floating-gate, thus reducing the floating-gate potential to shut off the floating-gate portion of the channel. Such high rate of electron absorption by the floating-gate due to the attractive floating-gate electric field enables the cell programming to be completed in a very short time (~1µs) with very low programming current (1-5µA). In contrast, in a traditional drain-side channel hot-electron (DS CHE) stack-gate flash cell, or similarly in an UV-EPROM cell, those lucky electrons, once generated, will face repulsive electric field from the floating-gate and only a very small portion of them with sufficient energy can make it to the floating-gate, resulting in very low efficiency programming. This is the reason why a DS CHE stack-gate cell requires much higher programming current than SuperFlash cell.

The SuperFlash® cell erases using poly-poly FN tunneling. With the floating-gate tip (or corner) functioning as a field enhanced tunneling injector, a lower voltage, comparing to stacked-gate flash cell, can be used on the word-line poly to erase the cell. Due to the low coupling ratio between the word-line poly and the floating-gate poly, a significant voltage drops across the tunneling oxide. A high electric field is localized along the edge of the tunneling injector, creating very fast charge transfer between word-line poly and floating-gate poly and the charge transfer eventually slows down when enough positive charges accumulated on the floating-gate. This accumulation of the positive charge on the floating-gate increases the floating-gate potential and determines the erased state "1" of the memory cell.

Simple Array Architecture and Design:

SST's SuperFlash® memory array is arranged in typical cross-point NOR architecture of rows (word-lines and source-lines) and columns (bit-lines). Each pair of word-line rows (odd and even) shares a common source-line. This arrangement enables small sector architecture which is suitable for applications such as smartcards.

There are two obvious advantages of SuperFlash® cell structure and erase operations that further simplify the peripheral circuitry design. The isolation of the floating-gate transistor from the drain with the select transistor prohibits the cell from being over erased. This helps to eliminate the need for complex extra circuitry required to correct over erased tail bits, a phenomena inherent in stacked-gate or nitride based memory cells. In addition, during erase, high voltage is only applied to the word-lines of selected pages, preventing erase disturb in unselected pages. This eliminates the need for erase disturb protection circuitry.

Employing extremely high efficiency SS CHE injection means that SuperFlash® array consumes very low programming current that can be sourced by a much smaller charge pump circuit relative to stacked-gate drain-side CHE programming.

There are 2 types of programming disturbs known to the split-gate memory cell that can easily be mitigated by proper design and optimized process: punch-through and reverse tunneling programming disturbs. The punch-through disturbs can be suppressed by inhibiting the unselected bit lines with Vcc (row punch-through) or by inhibiting the unselected word-lines with 0V (column punch-through). Reverse tunneling disturb can happen on the unselected erased cell, with inhibit bit line, that shares the same source line of the cell being programmed. This occurs when electrons are transferred from word-line poly to floating-gate poly. This disturb can be prevented with process optimization.

Low Power and High Performance:

SuperFlash® cell erase and program efficiency allows for small footprint of on-chip charge pump circuitry. This benefits both chip size and consumption power. In addition, the memory cell is read with low supply voltage without the requirement of a charge pump.

Low power consumption does not sacrifice SuperFlash® performance. Poly-to-poly FN tunneling with the enhanced tunneling injector enables very fast erase time, ~1ms. In addition to low programming current, SS CHE programs the split gate cell in ~1µs time. With such low power and millisecond write (erase and program) time, SuperFlash® has become the universal NVM solution for a large family of applications, ranging from wide temperature range with extremely low failure rate automotive micro-controllers to low power fast write time and high endurance smartcard designs.

CMOS Compatibility and Scalability:

The integration of SuperFlash® technology into baseline logic process is straightforward. In general, processing steps for memory cell and high voltage transistors required for erase and programming are formed before the formation of logic devices. This innovative integration keeps the baseline logic performance unchanged.

The ease of integrating high performance SuperFlash® memory cell into baseline CMOS logic process has made SST a strong and long lasting partner in embedded flash solution for some of the world leading foundries, in addition to several first tier IDM and fabless companies who are licensing the SuperFlash® cell. The scaling of the memory cell from 1µm to 65nm helps to maintain the continuity of a solid and reliable embedded NVM solution for our customers.

With such broad availability and the simple array architecture, the SuperFlash® cell is a superior solution for embedded application designers.

Excellent Reliability:

SuperFlash® cell inherits very high endurance capability. In general, loss of endurance is caused by charge trapping in the oxide during program/erase cycles. The trapped charges eventually degrade the memory cell erase and program efficiency. Due to the relatively low electric field, the oxide under the floating-gate near the gap injection region experiences minimal charge trapping. This results in almost no change in programming efficiency after several millions of cycles. During erase, the average electric field across the thick poly-to-poly tunneling oxide is low and the charge trapping generally is localized in a small region along and surrounding the tunneling injector tip. In real world usage where the memory cell is not cycled continuously, the charges trapped in the small oxide region surrounding the injector tip will get detrapped over time through direct tunneling.

Intrinsic data retention of SuperFlash® cell is very robust as a result of the two key factors of the split-gate cell structure. First, the oxide under the floating-gate poly is never exposed to high electric field due to the strong capacitive coupling, unlike that of a stacked-gate cell. Second, the inter-poly oxide used for erase is relatively thick and, the trap-free zone is wide enough to prevent electrons from tunneling through.

This is a key characteristic that protects SuperFlash® cell from inheriting SILC (stress induced leakage current), a reliability issue well known in the traditional stacked-gate flash memory cell. After several millions of program/erase cycles, the SuperFlash® cell does not exhibit any oxide leakage.

Summary:

High endurance, excellent data retention with extremely low failure rate, good performance at high temperature, and immunity to SILC have made SuperFlash® the embedded-flash of choice for automotive applications.

In addition to embedded applications for automotive electronics, SuperFlash® cell has also become a most popular choice for smartcard applications due to its fast write time (a few milliseconds) and access time, small-sector architecture, low power capability, and million-cycle endurance.

The ease of integrating high performance SuperFlash® memory cell into baseline CMOS logic process has made SST a strong and long lasting partner with several world's leading foundries and IDMs, allowing SST's SuperFlash® to be an attractive and dependable solution adopted by embedded flash system designers.