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What is SuperFlash?

SuperFlash is an innovate, highly reliable and versatile type of NOR Flash memory invented by SST. NOR is a form of random access nonvolatile memory that allows electronic systems to retain information when the power source is turned off. SST SuperFlash memory is much more flexible and reliable than other competing nonvolatile memories. SST SuperFlash technology utilizes a split-gate cell architecture which uses a robust thick-oxide process with fewer masking steps resulting in a low-cost nonvolatile memory solution with excellent data retention and higher reliability.

The SuperFlash split-gate memory cell is comparable in size to the single-transistor stacked-gate cell (for a given level of technology), yet provides the performance and reliability benefits of the traditional two-transistor Byte alterable EEPROM cell. By design, the SuperFlash split-gate memory cell eliminates the stacked gate issue of "over erase," by isolating each memory cell from the bit line. "Erase disturb" cannot occur because all Bytes are simultaneously erased in the same page and each page is completely isolated from every other page during any high-voltage operation.

The SuperFlash memory cell is a single-transistor split-gate memory cell using poly-to-poly Fowler-Nordheim tunneling for erasing and source-side channel hot electron injection for programming. Poly-to-poly tunneling is from a field enhancing tunneling injector formed on the floating-gate using industry standard oxidation and dry etching techniques. Source-side channel hot electron injection is very efficient, thus allowing the use of a small on-chip charge pump from a single low-voltage power supply, e.g. 5 or 3 volts. Cells are normally erased prior to programming.

The split-gate memory cell size is comparable to traditional stacked gate memory cells using the same process technology. This is possible because:

The tunneling injector cell does not need the extra spacing to isolate the high voltages required for programming the stacked gate array
Floating-gate extensions are not needed to achieve the required stacked gate coupling ratios.
Additionally, the simplicity of the cell structure eliminates many of the peripheral logic functions needed to control erasing of the stacked gate device. The tunneling injector cell can be formed using standard CMOS process. Memory arrays may use either random access or sequential access peripheral architectures.